1. Field of the Invention
The present invention relates to a multiple microprocessor intercommunication arrangement and, more particularly, to a multiple microprocessor intercommunication arrangement which permits two or more independently operating microprocessor units (MPUs) to sequentially access, under the control of synchronous clock signals, a common memory for either writing data therein or for reading data previously written therein without the need for continuous resolving means.
2. Description of the Prior Art
Systems incorporating multiple microprocessor units (MPUs) for processing system information almost invariably require an intercommunication channel between the various MPUs. Under conditions where two MPUs operate independently and require very little communication therebetween, a simple link comprising, for example, a peripheral interface adapter can be used to provide a single word path in each direction. Communication over such a link, however, would require control circuitry to permit each of the interconnected MPUs to be appropriately prepared to concurrently transmit and receive each byte to be passed therebetween, which is commonly termed "handshaking between MPUs". A simple link of this type creates no problem if processing time is plentiful or if the volume of traffic is very small.
Where other than a simple link is required, various arrangements have been devised to provide the necessary timing and control for multiple MPUs to gain access to the associated memory. For example, U.S. Pat. No. 3,715,729 issued to B. R. Mercy on Feb. 6, 1973 discloses a multiprocessor system having plural autonomous digital data processors operable to communicate individually with a common storage system. Each processor has its own clock, and a timing control means selectively uses any one of the individual processor clocks for timing the communication of its or any other processor with the common storage system. In another arrangement, U.S. Pat. No. 3,940,743 issued to B. P. Fitzgerald on Feb. 24, 1976 discloses a unit for interconnecting otherwise independently operable data processing systems. When one data processing system addresses the interconnecting unit, the unit acts like a peripheral device by converting the address to a physical memory address for the other data processing system. Furthermore the unit interrupts the other system to effect a data transfer either to or from the other system. Another arrangement is disclosed in U.S. Pat. No. 3,988,716 issued to J. C. Fletcher, et al. on Oct. 26, 1976 which relates to an interface logic circuit permitting the transfer of information between two computers having asynchronous clocks. The information transfer involves utilization of control signals to generate properly timed data strobe signals. Noise problems are avoided because each control signal, upon receipt, is verified by at least two clock pulses at the receiving computer. If control signals are verified, a data strobe pulse is generated to accomplish a data transfer. Once initiated the data strobe signal is properly completed independently of signal disturbances in the control signal initiating the data strobe signal. Completion of the data strobe signal is announced by automatic turn-off of a return-response control signal.
The foregoing prior art references are seen to function during the accessing of an MPU with the memory. Arrangements are also known which primarily function after the time that an MPU accesses the memory. In this regard see, for example, U.S. Pat. No. 3,886,525 issued to P. J. Brown, et al. on May 27, 1975 which discloses a data processing technique which permits a plurality of users of a data processing system to share data in a data store, thereby providing independent and asynchronous access to the data for subsequent processing by either user. The sharing of small data items is accomplished without requiring the use of interlocks to prevent one user from obtaining access to the shared data item while the other is processing the data for subsequent replacement in the shared data store.
The problem remaining in the prior art is to permit two or more MPUs to separately gain access to a memory in a communication channel therebetween without the need for contention resolving techniques.